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You are here: Home / ieee projects 2015 power electronics / IEEE 2015 Power Electronics Power Factor Correction Abstract Title List Topics

IEEE 2015 Power Electronics Power Factor Correction Abstract Title List Topics

September 21, 2015 by IeeeAdmin

S.NO TITLES ABSTARCTS Year
PEPF1 Optimal Lowest-Voltage-Switching for Boundary Mode Power Factor Correction Converters This paper presents an optimal lowest-voltage switching technique for boundary mode power factor correction (PFC) converters. The proposed approach minimizes the switching loss of the power MOSFET without additional discrete components. Optimal zero-voltage-switching or valley-switching can

be achieved for universal input range. The gate driver delay can

also be taken into account. A boundary mode boost PFC converter with the proposed optimal switching technique has been implemented using a 0.5-μm N-well process. Experimental results show

that the proposed approach can realize optimal soft switching, and improve the efficiency of the boost PFC converter. The proposed lowest-voltage-switching technique can be applied to other resonant converters as well.2015PEPF2A Three-Level Quasi-Two-Stage Single-Phase PFC Converter with Flexible Output Voltage and Improved Conversion EfficiencyThis paper presents a three-level quasi-two-stage single-phase power factor correction (PFC) converter that has

Flexible output voltage and improved conversion efficiency. The proposed PFC converter features sinusoidal input current, three level output characteristic, and a wide range of output dc voltages,

and it will be very suitable for high-power applications where the output voltage can be either lower or higher than the peak ac input voltage, e.g., plug-in hybrid electric vehicle charging systems. Moreover, the involved dc/dc buck conversion stage may only need

to process partial input power rather than full scale of the input power, and therefore the system overall efficiency can be much improved. Through proper control of the buck converter, it is also

Possible to mitigate the double-line frequency ripple power that is inherent in a single-phase ac/dc system and the resulting load end voltage will be fairly constant. The dynamic response of this

regulation loop is also very fast and the system is therefore insensitive

to external disturbances. Both simulation and experimental results are presented to show the effectiveness of this converter as well as its efficiency improvement against a conventional two-stage solution.2015PEPF3A Stepping On-Time Adjustment Method

for Interleaved Multichannel PFC ConvertersA simple and effective stepping on-time adjustment (SOTA) method with status judgment for interleaved multichannel

Critical mode (CRM) boost-type power factor correction (PFC) converters is proposed. The boost-type PFC converter with CRM operation is commonly used for ac–dc conversion because of its

Circuit simplicity and high efficiency. The interleaved multichannel PFC converter becomes the trend for high-power applications. However, conventional interleaved methods are complicated and

Difficult to implement when more than two channels are required. Also, noise disturbances or on-time mismatching can easily lead to continuous conduction mode operation which will increase current distortion, reduce power conversion efficiency, or even damage the converter. The proposed SOTA method with status judgment can

Greatly simplify the control complexity of the interleaved multichannel operation. A prototype 600-W three-channel interleaved CRM boost PFC converter is built to verify the performance of the proposed SOTA method.2015PEPF4Three-Level Single-Phase Bridgeless PFC RectifiersThis paper presents new three-level unidirectional single-phase PFC rectifier topologies well suited for applications

Targeting high efficiency and/or high power density. The characteristics

Of a selected novel rectifier topology including its principles of operation, modulation strategy, feedback control scheme, and a power circuit design related analysis are presented. Finally, a

220-V/3-kW laboratory prototype is constructed and used in order to verify the characteristics of the new converter, which include remarkably low switching losses and single ac-side boost inductor that allow for 98.6% peak efficiency with a switching frequency of 140 kHz.2015PEPF5A Fully Integrated Three-Level Isolated

Single-Stage PFC ConverterFor low-cost isolated ac/dc power converters adopting high-voltage dc-link, research efforts focus on single-stage multilevel topologies. This paper  ro poses a new single-stage three-level isolated ac/dc PFC converter for high dc-link voltage low-power applications,

achieved through an effective integration of ac/dc and dc/dc stages, where all of the switches are shared between two operations. With the proposed converter and switching scheme, input current shaping and output voltage regulation can be achieved simultaneously without introducing additional switches or switching actions. In addition, the middle two switches are turned on under

zero current in discontinuous conduction mode operation, and the upper and bottom switches are turned on under zero voltage. Due to the flexible dc-link voltage structure, high power factor can be achieved at high line voltage.A500 W/48Vprototype is designed to

serve as the proof of concept, which exhibits 90.8% peak efficiency

at low input line voltage.2015PEPF6A Digitally Controlled Critical Mode Boost Power Factor Corrector With Optimized Additional On Time and Reduced Circulating LossesIn many low-to-mid power applications, critical mode boost power factor corrector converters are widely used because of its low switching loss and simple control. However, near the zero

Crossing of the input line voltage, an input current distortion and a low power factor are caused by delayed switching period and negative input currents. Generally, an additional on-time method

According to the input voltage is used to compensate the input current distortion. However, a detailed quantitative analysis for the exact additional on time has not been studied till now. In this paper, the explicit form of the optimized additional on time has been obtained using a quantitative analysis and the advantage of the digital control. From a state trajectory and “net input charge”

Analysis, it is shown that the optimized on time should be related to not only the input voltage, but also the output power. Also, in order to improve the efficiency in a high input and light load condition, circulating currents are reduced in the inevitable dead angle with a gate turning-off technique. By using digital control, the

Optimized additional on time and the gate turn-off technique have been implemented with the 90–230 Vrms input and 380 V/200 W output prototype.2015PEPF7Bridgeless PFC-Modified SEPIC Rectifier With Extended Gain for Universal Input

Voltage ApplicationsIn this paper, a new single-phase ac–dc PFC bridgeless rectifier with multiplier stage to improve the efficiency at low

Input voltage and reduce the switch-voltage stress is introduced. The absence of an input rectifier bridge in the proposed rectifier and the presence of only two semiconductor switches in the current flowing path during each switching cycle result in less conduction

losses and improved thermal  management compared to the conventional full bridge topology. Lower switch voltage stress allows utilizing a MOSFET with lower RDS-on. The proposed topology is designed to operate in discontinuous conduction mode (DCM) to achieve almost a unity power factor and low total harmonic distortion (THD) of the input current. The DCM operation gives additional advantages such as zero-current turn-on in the power switches and simple control circuitry. The proposed topology is compared with modified full-bridge SEPIC rectifier in terms of efficiency, THD, and power factor. Detailed converter analysis, small

Signal model, and closed-loop analysis are presented. Experimental

Results for a 200 W/400 Vdc at universal line voltage range to evaluate the performance of the proposed bridgeless PFC rectifiers are detailed.2015PEPF8Time-Varying Compensation for Peak

Current-Controlled PFC Boost ConverterIn this paper, an optimal time-varying compensation method with zero eigenvalue is first put forward for peak current controlled power factor correction (PFC) boost converter, which can eliminate the fast-scale instability without zero current dead zone and achieve unity power factor. First, a time-varying mathematic model of a peak current-controlled PFC boost converter

under continuous conduction mode is established. Then, based on the theoretical and experimental analyses of the traditional ramp compensation, a time-varying dynamic compensation model and method are presented to obtain zero eigenvalue during the

whole life cycle. Therefore, the PFC boost converter occupies the strongest stability control during each switching cycle and can run into stable operation in one switching cycle under any external interference. Finally, the proposed compensation method is verified

with experiments. Results show that a unity power factor and the stability in the whole line cycle can be obtained simultaneously.2015

ieee 2015 power electronics power factor correction project titles

ieee 2015 power electronics power factor correction project titles

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